SiFive is the first fabless semiconductor company to build customized silicon based on the free and open RISC-V instruction set architecture. For the chip design contest, they need to have a team capable of doing RTL synthesis using CHISEL (ie in Scala Language). Chisel is a relatively new language hence finding talent is arduous. Hence TrEST Park is planning to initiate an internship programme to hire a minimum of 4 paid research interns at TrEST Research Park for the Chisel Development Group. If the interns prove productive enough, TrEST may hire them for one full year on a contract basis to work full time on the design contest.
Details and Requirements of RISC-V Internship are as follows:-
Its basically a RISC – V internship for 4 students of 2-3 months duration. Interns will be paid an amount of Rs.8000 as their stipend during the internship period. Work location will include Trivandrum and Bangalore.
M.Tech in VLSI/ Related Course or B.Tech in Electronics/Electrical/Computer Science Engg (Including pass outs). Students should secure 70% aggregate in their 10th and 12th.
Skills Required :
- Good Quantitative and Logical Reasoning skills.
- Hands on debugging experience using CRO, DSO, Function Generator and DMM.
- Excellent Programming Skills, preferably functional programming.
- Knowledge of Hardware Peripheral Interfaces such as SPI, I2C.
- Excellent Communication Skills, social skills, a team player.
- Ability to work in an AGILE environment.
Selection Process :
Screening and One to One Interview.
Scope of work:
Candidates are expected to work in a highly challenging environment to prototypes/ logic design using Scala (CHISEL) and Verilog.
- Candidates who deliver may be appointed at TrEST Research Park on a 1 Year Contract.
- The candidates may also be offered with permanent positions by companies such as Open Silicon, ARM etc.
COLLEGE OF ENGINEERING TRIVANDRUMwww.cet.ac.in
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