Trivandrum Engineering Science & Technology Research Park

An Institution of Government of Kerala

TrEST ERC’s Fabless CoE

TrEST ERC’s Fabless CoE

What is Fabless semiconductor Technology?
A fabless company is an electronic chip (IC) company that does not own a semiconductor foundry. The term ‘fab’ stands for fabrication, hence, ‘fabless’ indicating that the company does not take any part in the fabrication of the product but instead only participates in the designing and marketing aspects of the semiconductor chips.

The fabless model of semiconductor chip production has become a popular solution for cost-management in an industry that is notoriously expensive. Fabless companies design the chips and work with foundries (like Taiwan’s TSMC , US based Global foundries etc.) to manufacture them – a collaboration that is extremely cost-effective for fabless designers. New, leading edge fabrication facilities cost billions of dollars to build and keep up-to-date, representing a financial barrier that most chip designers find impossible to surmount.

The Fabless model has proved to be successful and gave birth to many new semiconductor companies. Today majority of world’s semiconductor chip makers are fabless companies like NVIDIA, AMD, Qualcomm, TI, NXP and Broadcom.

Fabless technology in Indian Context – A strategic necessity

Having a fabless semiconductor ecosystem is extremely important for India. India has been taking quiet but tentative steps towards indigenous chip design capability for a few years now despite the many teething problems, as it looks at home-grown chip development as a strategic necessity.

China, for example, is building a home-grown chip programme, eyeing adoption of local semiconductors in 70% of its products by 2025, up from 16% currently.

India, for its part, is seeking to create a home-grown fabless semiconductor design ecosystem as it realizes that make-in-India objectives cannot be achieved without designing chips that make-up significant portion of the cost of our electronic hardware imports.

According to India Electronics and Semiconductor Association(IESA), the Indian semiconductor design ecosystem is quite robust, with most of the major global semiconductor players having their R&D centres in India. In addition to global R&D centres by semiconductor giants like Intel, Qualcomm, Broadcom and NVIDIA, the past decade has seen quite a few Indian entrepreneurs starting their own fabless IP or SoC design houses. India is a highly attractive destination for global R&D centres owing to the availability of talent, as well as lower cost (compared with the US and Western Europe).

The ingredients are available in the country to build a robust fabless semiconductor ecosystem and this requires connecting with talent pool, accelerating investment promotions, getting into international alliances and lastly policy implementations.

Most important aspect here is talent pool. Though there has been much progress compared to last decade, Indian fabless industry is still lagging significantly when it comes to talent pool available. Electronic engineering academic syllabus for majority of Indian universities are not up to speed with developments happening in this industry. As a result, there are no sufficient industry-ready chip designers coming out of academic institutions. There is a strong gap exists in achieving the Indian objective of fabless semiconductor ecosystem.

College of Engineering Trivandrum (CET) & TrEST ERC’s Fabless CoE

From a Kerala point of view, it is extremely important to be part of this strategic fabless eco-system. Creating a fabless semiconductors talent pool can attract significant investments in Kerala. All major semiconductor giants are setting up centres in Bangalore and Hyderabad. Kerala has already made significant progress as a software service business destination. Kerala can attract high technology semiconductor investments from global leaders too. But, Kerala’s academic institutions need to produce skilled engineers in hardware and fabless technology to become an attractive semiconductor design destination. Founded in 1939 by erstwhile Maharaja of Travancore, CET is one of the premier engineering institutions in Kerala which has been producing very talented engineers and industrial leaders. Being situated in Trivandrum along with premier public sector R&D houses like VSSC and CDAC, College of Engineering Trivandrum(CET) is ideally suited for taking leadership in national hardware and fabless objectives.

RISC-V chip project for TrEST ERC Fabless CoE program

Objective of this project is to develop a RISC-V processor chip and associated tool chain through participation between CET, public research organisations and private industry under the TrEST ERC program. In the process, TrEST will be enabling students, faculties and local industrial ecosystem to demonstrate an operational model that caters high-tech research participation between industry and academia in Kerala. RISC-V is an open ISA (instruction set architecture) enabling a new era of innovation for processor architectures.

Significance of TrEST ERC’s RISC-V project

Today’s RISC-V eco-system is driven mainly by open-source versions maintained by international research organizations like Berkeley. The processor has great significance for India’s interests for both civilian and defence needs. For RISC-V to be qualified for these needs, the processor core has to go through very extensive verification and testing. TrEST’s ERC is taking this as a problem statement.

Kerala’s academic sector will benefit heavily by working on a strategic and industrial problems. Solving it end-to-end by working under expert guidance and strict quality guidelines will give a lot of knowledge to the students as well as faculties. This is an important piece many academic projects are significantly missing. The RISC-V project will create a huge value for the students and faculties in gaining true industrial design skills.

Key Technologies for the RISC-V chip program

The RISC-V project requires multi-disciplinary skills that can be broadly categorized as follows

  • Architecture
  • Front-end design implementation.
  • Front-end design verification.
  • FPGA System validation
  • Chip System validation (SV).
  • RTL-GDS Back-end – Structural design(SD) & physical verification (PV)
  • PCB design and fabrication.
  • Software co-simulation
  • Embedded software and Compiler design.

Key Activities

TrEST’s Fabless Technology partner – Westghats Technologies
Westghats is a fabless semiconductor company developing hardware acceleration chipsets to enable edge computing for several high potential computer vision and AI applications. The company is founded by former Intel, Conexant and CDAC engineers with vast experience in semiconductor industry. They are building a neural processing chip-architecture that provides best performance per power for battery powered edge devices to achieve high efficiency in computer vision & AI processing. The company also provide architecture and design consultancy services to SoC design houses license Silicon intellectual property (IP) cores to them and enable them in SoC integration and tape-out to achieve silicon success. Their customers include Japanese Tier1 automotive companies and California based wireless (IoT and Multimedia) semiconductor chip makers. Westghats will be the key mentor and technology partner for the TrEST ERC’s RISC-V & fabless CoE program.

Career as a Chip Developer

TrEST Research Park is recruiting Junior Research Fellows to work along with faculty, and students of CET as well as Westghats Technologies, the technology partner. Visit the for more details.

College of Engineering Trivandrum

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