Webinar on Analog IC Design Flow Using Cadence EDA Tools
TrEST Research Park, in collaboration with Entuple Technologies, successfully conducted a specialized webinar on “IC Design Flow Using Cadence EDA Tools.” The session was led by Mr. Rakesh B R, Field Application Manager, who provided expert insights into industry-relevant design methodologies and workflows.
The webinar offered a comprehensive overview of the full custom IC design flow, covering key stages such as MOSFET characterization, schematic capture, symbol creation, testbench development, and functional simulation using Spectre. Participants were also introduced to layout design techniques and physical verification processes, enabling a deeper understanding of end-to-end chip design.
In addition, the session included an overview of the semi-custom design flow, highlighting functional verification and physical implementation using Cadence Innovus. A CMOS inverter case study was utilized to demonstrate the complete analog design flow, bridging theoretical concepts with practical application through hands-on demonstrations.
This initiative significantly contributed to enhancing participants’ competencies in VLSI design methodologies, equipping them with practical knowledge and exposure to industry-standard Cadence EDA tools.
